Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell holds a certain level of a given physical quantity such as an electrical charge or voltage, which represents the data stored in the cell. The levels of this physical quantity are also referred to as analog storage values or analog values. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to a programming state or programming level that represents one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate,” Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
Analog memory cells, such as Flash memory cells, are typically read by comparing the analog cell values to one or more read thresholds. Various techniques for setting and adjusting read thresholds are known in the art. For example, U.S. Pat. No. 5,657,332, whose disclosure is incorporated herein by reference, describes methods for recovering from hard errors in a solid-state memory system. A memory system includes an array of memory cells, each cell capable of having its threshold voltage programmed or erased to an intended level. An error checking scheme is provided for each of a plurality of groups of cells for identifying read errors therein. A read reference level is adjusted before each read operation on the individual group of cells containing read errors, each time the read reference level being displaced a predetermined step from a reference level for normal read, until the error checking means no longer indicates read errors. The drifted threshold voltage of each cell associated with a read error is re-written to its intended level.
U.S. Patent Application Publication 2007/0091677, whose disclosure is incorporated herein by reference, describes techniques for reading data from one or more Flash memory cells, and for recovering from read errors. In some embodiments, in the event of an error correction failure by an error detection and correction module, the Flash memory cells are re-read at least once using one or more modified reference voltages, until successful error correction may be carried out.
U.S. Pat. No. 6,963,505, whose disclosure is incorporated herein by reference, describes methods for determining a reference voltage. In some embodiments, a set of operating reference cells is established to be used in operating cells in a Non-Volatile Memory (NVM) block or array. At least a subset of cells of the NVM block or array may be read using each of two or more sets of test reference cells, where each set of test reference cells may generate or otherwise provide reference voltages at least slightly offset from each other set of test reference cells. For each set of test reference cells used to read at least a subset of the NVM block, a read error rate may be calculated or otherwise determined. A set of test reference cells associated with a relatively low read error rate may be selected as the set of operating reference cells to be used in operating other cells, outside the subset of cells, in the NVM block or array.
U.S. Patent Application Publication 2010/0091535, whose disclosure is incorporated herein by reference, describes various techniques for adjusting read thresholds of analog memory cells. In one of the disclosed techniques, data is encoded with an Error Correction Code (ECC) before it is stored in the memory cells. When retrieving data from the memory cells, the ECC is decoded in order to correct read errors. For a given read error that was corrected by the ECC, the direction of the error, i.e., the programming level with which the read storage value was erroneously associated before applying ECC correction, is determined Information regarding directions of corrected errors is used for adjusting the read thresholds.
U.S. Patent Application Publication 2012/0063227, whose disclosure is incorporated herein by reference, describes a system and method for adjusting read threshold voltage values, for example, in a read circuit internal to a memory device. The quality of an associated read result may be estimated for each read threshold voltage value used to read memory cells. Only read results estimated to have sufficient quality may be allowed to pass to storage. The read threshold voltage value may be adjusted for subsequent read operations, for example, if the associated read result is estimated to have insufficient quality. The read threshold voltage value may be iteratively adjusted, for example, until a read result is estimated to have sufficient quality.